DueProLogic USB-FPGA Development System

FPGA Training

The DPL gives learners the opportunity to have an appropriate hands-on approach when learning logic, exploring different iterations of schematic/code designs with simple uploads of the design, and the operation of those circuits with relatively easy runtime passing of project parameters and data, and an abundance of headers that can interface to external components, without having to spend inordinate amounts of time reading datasheets, designing the right combinations of gates on multi-gate chips, and building/revising/debugging/revising repeatedly… spaghetti bowls of wires and chips on multiple breadboards to connect to those same external components. With the DPL’s FPGA, projects can also more easily be attempted which rely on asynchronous, exceedingly fast, and even multiple separate concurrent logic structures operating in parallel which would have traditionally required a plethora of chip gates or multiple high speed microprocessors to implement parallel processes. Logic circuits are implemented within the FPGA at few-nanosecond gate speeds and highly parallel in operation, effectively a few hundred MHz; Microprocessors often rely on inherently slower single threaded program loops with interrupt servicing, which is typically much slower. Programmable logic is today’s technology for logic learners and implementers, replacing discrete logic chips.

DueProLogic Overview

The DPL is a complete FPGA development environment. It includes a powerful Altera Cyclone IV FPGA, High-Speed USB interface chip, Full SD Card interface connector, and 4Mb Configuration Flash (for the FPGA). The USB interface chip is an FT2232H with Dual Serial Channels. One channel is dedicated to loading the configuration Flash for the FPGA. The second channel provides a high speed interface for bi-directional communications with the FPGA. Once the configuration Flash is loaded with the users synthesized code, a reset will cause the FPGA to read the Flash and load up the stored image into the FPGA.

The block diagram shows all of the parts of the DueProLogic. There are two main power supplies, +1.2V and +3.3V. The +1.2V powers the core of the FPGA while the +3.3V powers the Input/Outputs of the FPGA as well as provides power for user circuits. The DPL contains two oscillators, 66MHz and 100MHz. The 66MHz oscillator is used to provide clocking for the EPT ActiveHost USB communications core. The 100MHz oscillator can be used by the user clocked up using one of the onboard Clock-DLL modules.

6×6 LED Array

Development Environment

The DueProLogic includes a 6×6 Green LED array. Each LED is sinked to an individual pin on the FPGA. Each LED is current limited to 6mA. The total current consumed for all 36 LEDs is 216mAs. The FPGA can easily sink this current. So, individually sinking all 36 LEDs makes easy control for User Code. The DueProLogic also contains a method to turn on/off the LEDs in four unit blocks. A jumper is used to control the state of each LED block.

DueProLogic Block Diagram

Development Environment

The DPL User Manual comes complete with instructions to set up all the drivers, the Altera Quartus development environment, and get started creating FPGA projects. The User Manual walks the user step by step from start to finish of the first FPGA project.

The included Windows development environment kit includes: Quartus II for compiling user code, assigning pins, project setup, programming and other items. The kit also includes the EPT ActiveHost core for the DPL, to facilitate communication between the PC and DPL while the DPL is running a developed project. The kit also EPT has developed a .dll that allows Quartus II to directly program the DPL in the same way USB-Blaster works with other Altera populated development boards.

• Quartus Prime Lite for Windows, which is the Altera Programmable Logic development environment allowing for the development, simulation, and debugging of FPGA code by drawing logic schematics or by using Verilog or VHDL (and other variants) hardware description language (HDL), open core modules, and more specific Intellectual Property (IP) from EPT and others.
• Within the Quartus environment, EPT supplies the EPT_Blaster.dll that allows Quartus Prime Lite to directly program the DPL in the same way Altera’s USB-Blaster works with other Altera populated development boards.
• The EPT GUI/Data Transfer Library .dll for Windows that allows applications developed with Microsoft’s Visual Studio Express (and others) PC application development environments, to communicate with the DPL at runtime using a GUI interface.
• The EPT File Transfer core for the DPL, which is the code that resides within the DPL’s Cyclone FPGA to allow run-time data exchange with the PC.
• The sum is a very rich development environment for the DPL. A comprehensive user setup and use manual and sample projects with code are available on the EPT website.

Configuring the FPGA

The FPGA on the DPL can be programmed with the HDL project created by the user. Configuration is quick and easy. All that is required is a standard USB cable with a USB-C connector, and the EPT Blaster Driver DLL installed on the PC. There are no extra parts to buy – just plug in the USB cable and connect the DueProLogic to the PC.

The DPL Configuration Flash is programmed using the Quartus development environment and the EPT Blaster Driver. Once the the Configuration Flash is programmed. A reset will cause the FPGA to begin configuring itself using the Flash.

Installing the Terranologic Quartus DLL

To program the DueProLogic FPGA, the Terranologic USB Blaster *.dll must be added to the quartus64/bin folder of the root of the Quartus installation. Terranologic has an automated installer that will add the *.dll to the appropriate location.

Double click on the Terranologic_USB_Blaster_Installer.zip. The web browser will download the zip file. The web browser will automatically download the zip file. When download is complete, double click on the zip file.

When the dialog box appears, double click on the EPTInstaller.exe file

The following message will appear:

Click on the “Extract all” button and follow the installation messages. Next, the following window appears. This window will ensure that the user transfers the *.dll file into the appropriate Quartus folder with full Administrator Privleges.

Click “Yes”. If the user has full Administrator Privileges, the *.dll file will be copied correctly. If the user does not have Administrator Privileges, then you will have to determine how to get these Privileges.

Once the installation is complete, you will see the following message.

Click “OK”. Open the Quartus Application. The DLL is installed and the Quartus JTAG server should recognize it. Go to Programmer and locate the EPT-JTAG-Blaster v1.0 (64).

The DueProLogic is ready to be programmed using Quartus Prime Software.

Platform Demonstration Software

The board comes preloaded with the Platform Demo project. This Verilog based
project has several functions that allow the user to exercise the various hardware included on the DPL. Also included with the product is a DVD with the needed PC/Quartus/DPL drivers, library, User Manual, Schematics, and sample projects. All the documentation is available on the EPT web site for download.

Downloads