m255
K4
z2
!s11f vlog 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/ModelSim
vactive_block
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8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_block.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_block.v
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!s85 0
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!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_block.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_block.v|
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vactive_control_register
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!i10b 1
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R0
R4
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_control_register.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_control_register.v
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r1
!s85 0
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!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_control_register.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_control_register.v|
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vactive_serial_library
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FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_serial_library.v
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r1
!s85 0
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!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_serial_library.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_serial_library.v|
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R7
R8
vactive_transfer
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IQ0HLGM[<MLY7eTg4z;0=C2
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R0
R4
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_transfer.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_transfer.v
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r1
!s85 0
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!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_transfer.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_transfer.v|
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R7
R8
vactive_transfer_uart
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FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_transfer_uart.v
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r1
!s85 0
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!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_transfer_uart.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_transfer_uart.v|
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R6
R7
R8
vactive_trigger
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R0
R4
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_trigger.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_trigger.v
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r1
!s85 0
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!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_trigger.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/active_trigger.v|
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R7
R8
vadc_model
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R0
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FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/adc_model.v
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r1
!s85 0
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!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/adc_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/adc_model.v|
!i113 1
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R8
vcounter_53
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!i10b 1
!s100 E_35z>?1[=V^RXcbWYXf>1
R2
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R3
R0
R4
Z15 8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/serial_uart_comms_model.v
Z16 FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/serial_uart_comms_model.v
!i122 1629
L0 580 10
R5
r1
!s85 0
31
!s108 1784319669.000000
Z17 !s107 ../Testbench/tb_define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/serial_uart_comms_model.v|
!s90 -reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/serial_uart_comms_model.v|
!i113 1
R6
R8
vendpoint_registers
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!i10b 1
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R0
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8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/endpoint_registers.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/endpoint_registers.v
!i122 1685
L0 38 715
R5
r1
!s85 0
31
R12
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/endpoint_registers.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/endpoint_registers.v|
!i113 1
R6
R7
R8
vEPT_5M57_AP_U2_Top
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!i10b 1
!s100 Y?nd[j;6BYn@kVE>c<k9G2
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R0
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8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/EPT_5M57_AP_U2_Top.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/EPT_5M57_AP_U2_Top.v
!i122 1686
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r1
!s85 0
31
R12
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/EPT_5M57_AP_U2_Top.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/EPT_5M57_AP_U2_Top.v|
!i113 1
R6
R7
R8
n@e@p@t_5@m57_@a@p_@u2_@top
veptWireOR
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!i10b 1
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R2
IR2LZ[`_5jC8ZSCdXdBAhJ1
R3
R0
w1341557582
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/eptWireOR.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/eptWireOR.v
!i122 1687
L0 32 14
R5
r1
!s85 0
31
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!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/eptWireOR.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/eptWireOR.v|
!i113 1
R6
R7
R8
nept@wire@o@r
vfifo_4x16_model
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!i10b 1
!s100 l9RzhGh>bI66SDmAFPXgA2
R2
I7YNigY<KcQfPiZH@nSmz<0
R3
R0
R4
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/fifo_4x16_model.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/fifo_4x16_model.v
!i122 1706
L0 38 328
R5
r1
!s85 0
31
R14
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/fifo_4x16_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/fifo_4x16_model.v|
!i113 1
R6
R7
R8
vflipflop
!s110 1784319655
!i10b 1
!s100 KQF:E_R5;LHg^QW[fz]1G2
R2
IKZnWG221efQR9PblB1@cG3
R3
R0
w1373324110
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/flipflop.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/flipflop.v
!i122 1605
L0 12 25
R5
r1
!s85 0
31
!s108 1784319655.000000
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/flipflop.v|
!s90 -reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/flipflop.v|
!i113 1
R6
R8
vft_245_state_machine
R18
!i10b 1
!s100 X[0z5G:Q0hh`iTn=eJcUM2
R2
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R3
R0
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8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/ft_245_state_machine.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/ft_245_state_machine.v
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r1
!s85 0
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!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/ft_245_state_machine.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/ft_245_state_machine.v|
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R6
R7
R8
vhost_ft245_model
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!i10b 1
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R2
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R3
R0
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FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model.v
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r1
!s85 0
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!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model.v|
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R7
R8
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!i10b 1
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R3
R0
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8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model_read.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model_read.v
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r1
!s85 0
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!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model_read.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model_read.v|
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R7
R8
vhost_ft245_model_write
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FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model_write.v
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r1
!s85 0
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R14
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model_write.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_ft245_model_write.v|
!i113 1
R6
R7
R8
vhost_image_block_in
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!i10b 1
!s100 Ejk@4T`:X89RFKakUZ?_32
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R3
R0
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8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_image_block_in.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_image_block_in.v
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r1
!s85 0
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!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_image_block_in.v|
!s90 -reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/host_image_block_in.v|
!i113 1
R6
R8
vmax11618_adc_model
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!i10b 1
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I=Amf3PAoO=6@mPY]8CKWP1
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R0
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8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/max11618_adc_model.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/max11618_adc_model.v
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R5
r1
!s85 0
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!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/max11618_adc_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/max11618_adc_model.v|
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R7
R8
vmem_array
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FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/mem_array.v
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r1
!s85 0
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R21
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/mem_array.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/mem_array.v|
!i113 1
R6
R7
R8
vmux
R18
!i10b 1
!s100 cfIo4h^n17Y<38i_4hcXS0
R2
IT:=9U5<XR36P7:SI>EHjQ3
R3
R0
w1373323066
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/mux.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/mux.v
!i122 1690
L0 12 21
R5
r1
!s85 0
31
R19
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/mux.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/mux.v|
!i113 1
R6
R7
R8
vread_control_logic
Z22 !s110 1784348930
!i10b 1
!s100 2bkeFNH6gb3PoaPH::Ven2
R2
I<g<2j28A@@iQVcR>c8o6`3
R3
R0
w1331918130
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/read_control_logic.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/read_control_logic.v
!i122 1711
L0 14 57
R5
r1
!s85 0
31
R21
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/read_control_logic.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/read_control_logic.v|
!i113 1
R6
R7
R8
vread_SPI
Z23 !s110 1784348926
!i10b 1
!s100 oh2Ycj^ULgN0ZlZ>SKbCN0
R2
IOz<?c^4jY_62NCYQR9dU?0
R3
R0
w1432850392
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/read_SPI.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/read_SPI.v
!i122 1692
L0 16 235
R5
r1
!s85 0
31
Z24 !s108 1784348926.000000
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/read_SPI.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/read_SPI.v|
!i113 1
R6
R7
R8
nread_@s@p@i
vserial_clock
R23
!i10b 1
!s100 5=E=U]G8Kj;c;VU__bYHA2
R2
I?7:VPh[XmWIlN;>bGzk@z1
R3
R0
R4
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/serial_clock.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/serial_clock.v
!i122 1693
L0 30 49
R5
r1
!s85 0
31
R24
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/serial_clock.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/serial_clock.v|
!i113 1
R6
R7
R8
vserial_uart_comms_model
R22
!i10b 1
!s100 1P5HzL]Ro[@UzD?=`fCFC1
R2
I=@?<GX9nf^12^G_[8CQj<1
R3
R0
R11
R15
R16
!i122 1714
L0 40 537
R5
r1
!s85 0
31
Z25 !s108 1784348930.000000
R17
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/serial_uart_comms_model.v|
!i113 1
R6
R7
R8
vspi_iface_model
R23
!i10b 1
!s100 HRTPj?M`XflHkd;?A71oG0
R2
I<6aU3>j4=l8YIH:GgNGK60
R3
R0
w1439627996
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/spi_iface_model.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/spi_iface_model.v
!i122 1694
L0 14 447
R5
r1
!s85 0
31
R24
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/spi_iface_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/spi_iface_model.v|
!i113 1
R6
R7
R8
vspi_interface
R23
!i10b 1
!s100 ZR@_8:HN=<7ZEC2o34DBO2
R2
IJU=V3Xf>G9Y<D=__Wi5K=1
R3
R0
w1434686059
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/spi_interface.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/spi_interface.v
!i122 1695
L0 14 548
R5
r1
!s85 0
31
R24
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/spi_interface.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/spi_interface.v|
!i113 1
R6
R7
R8
vspi_slave
R20
!i10b 1
!s100 gOeoLLz6C2M3Gb8De`9SO1
R2
I0oenzTdda1S_Z?B4=H80W0
R3
R0
w1640846696
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/spi_slave_model.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/spi_slave_model.v
!i122 1708
L0 15 628
R5
r1
!s85 0
31
R21
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/spi_slave_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/spi_slave_model.v|
!i113 1
R6
R7
R8
vspi_tiny_slave_model
R20
!i10b 1
!s100 DG<<bjzV75QCnl@hm_Z^b3
R2
I06VVl<4JIFWVRiU`Un^ML2
R3
R0
w1640846750
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/spi_tiny_slave_model.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/spi_tiny_slave_model.v
!i122 1709
L0 15 496
R5
r1
!s85 0
31
R21
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/spi_tiny_slave_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/spi_tiny_slave_model.v|
!i113 1
R6
R7
R8
vsync_fifo
R22
!i10b 1
!s100 4XVYIXkQJNZ9P`foKLHRV3
R2
Ig`L_[oQc32Z8PNVBAmCgT2
R3
R0
w1331919792
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/sync_fifo.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/sync_fifo.v
!i122 1713
L0 12 82
R5
r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/sync_fifo.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/sync_fifo.v|
!i113 1
R6
R7
R8
vtb_ept_epm570_top
Z26 !s110 1784348931
!i10b 1
!s100 @`]aTUSzKn2EX_naZcG4f0
R2
I7^=54=b<0N2;Q6NgU75IG0
R3
R0
w1784101168
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/Testbench/tb_ept_epm570_top.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/Testbench/tb_ept_epm570_top.v
!i122 1719
L0 32 1926
R5
r1
!s85 0
31
Z27 !s108 1784348931.000000
!s107 ../Testbench/tb_define.v|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/Testbench/tb_ept_epm570_top.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/Testbench/tb_ept_epm570_top.v|
!i113 1
R6
R7
R8
vuart_iface
R22
!i10b 1
!s100 Gh4X3;]TjR0EPU^n0GgF60
R2
If@0j`;[knV7`EXNOAm6Of0
R3
R0
Z28 w1614731351
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_iface.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_iface.v
!i122 1715
L0 36 59
R5
r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_iface.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_iface.v|
!i113 1
R6
R7
R8
vuart_receiver
R26
!i10b 1
!s100 CaEIJ[QP1QWC5ehWLdEYL1
R2
IXV1WS4hae61J_VGifnLIO0
R3
R0
R28
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_receiver.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_receiver.v
!i122 1716
L0 11 239
R5
r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_receiver.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_receiver.v|
!i113 1
R6
R7
R8
vuart_top
Z29 !s110 1784348927
!i10b 1
!s100 =<3>;QbRd[3U=Z>_cEmUS2
R2
IJmAU`5MDTP]QaMbHd9NQR0
R3
R0
R4
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/uart_top.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/uart_top.v
!i122 1698
L0 24 57
R5
r1
!s85 0
31
Z30 !s108 1784348927.000000
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/uart_top.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/uart_top.v|
!i113 1
R6
R7
R8
vuart_transmitter
R29
!i10b 1
!s100 XDo:jUIJ1`66X5E33Ho:l2
R2
I0cLCPU;`HJAf3[F9QaJb]1
R3
R0
R4
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/uart_transmitter.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/uart_transmitter.v
!i122 1699
L0 22 180
R5
r1
!s85 0
31
R30
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/uart_transmitter.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/uart_transmitter.v|
!i113 1
R6
R7
R8
vuart_transmitter_model
R26
!i10b 1
!s100 5[afZUQ]z0?WT5neSCX7b2
R2
IP@Pna;Lb9<S@F^;hTQ<<l2
R3
R0
R28
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_transmitter_model.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_transmitter_model.v
!i122 1717
L0 23 180
R5
r1
!s85 0
31
R27
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_transmitter_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/uart_transmitter_model.v|
!i113 1
R6
R7
R8
vwrite_control_logic
R26
!i10b 1
!s100 ZZfUVoPnGLV?1heZLf^lH2
R2
ImA?URPlFZ79eelcGVGX3C2
R3
R0
w1328652014
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/write_control_logic.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/write_control_logic.v
!i122 1718
L0 14 68
R5
r1
!s85 0
31
R27
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/write_control_logic.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/test/write_control_logic.v|
!i113 1
R6
R7
R8
vwrite_SPI
R29
!i10b 1
!s100 lOh]B:8OnnQK6CDiL]GWR2
R2
IDTANQ5`NfNGUk;@7hD^DZ1
R3
R0
w1439628013
8C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/write_SPI.v
FC:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/write_SPI.v
!i122 1701
L0 16 207
R5
r1
!s85 0
31
R30
!s107 C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/write_SPI.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_5M57_AP_U2_UnoProLyzer/EPT_5M57_AP_U2_UnoProLyzer/src/write_SPI.v|
!i113 1
R6
R7
R8
nwrite_@s@p@i
