m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/ModelSim
vactive_transfer_serial
!s110 1573599083
!i10b 1
!s100 C0;5SYP:7VmU[Dh_;NeoF1
I4i<HNhW2S_ZlzVLH3]gk80
Z1 VDg1SIo80bB@j0V0VzS_@n1
R0
w1527808486
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/active_transfer_serial.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/active_transfer_serial.v
Z2 L0 33
Z3 OV;L;10.5b;63
r1
!s85 0
31
!s108 1573599083.000000
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/active_transfer_serial.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/active_transfer_serial.v|
!i113 1
Z4 o-work work
Z5 tCvgOpt 0
varray_compare
Z6 !s110 1573599081
!i10b 1
!s100 LF8W5ZFL`9HF;Z>RVP2><0
IURLjc29AHT<:n5P]1HmGK0
R1
R0
w1527897902
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/array_compare.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/array_compare.v
R2
R3
r1
!s85 0
31
Z7 !s108 1573599081.000000
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/array_compare.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/array_compare.v|
!i113 1
R4
R5
vbutton_control
Z8 !s110 1573599084
!i10b 1
!s100 ^DBQY=Q4IcK6n4=_cS5HA2
I850WI7S`6hOliNoceaCIE3
R1
R0
w1527645504
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/button_control.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/button_control.v
Z9 L0 13
R3
r1
!s85 0
31
Z10 !s108 1573599084.000000
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/button_control.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/button_control.v|
!i113 1
R4
R5
vcommand_parse
!s110 1573599080
!i10b 1
!s100 NLoCBKdnBA;J@Y@XjmKcA0
IJ7:oXRSIzz7i;mKfZkoho2
R1
R0
w1528250536
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/command_parse.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/command_parse.v
R2
R3
r1
!s85 0
31
!s108 1573599080.000000
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/command_parse.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/command_parse.v|
!i113 1
R4
R5
vEPT_10M04_AF_S2_Top
Z11 !s110 1573707473
!i10b 1
!s100 W0JF0Ge5CKSmncfnm0h=81
I0fZfH<M11R:MzTefck;ZY3
R1
R0
w1573707469
8../../EPT_10M04_AF_UART/src/EPT_10M04_AF_S2_Top.v
F../../EPT_10M04_AF_UART/src/EPT_10M04_AF_S2_Top.v
L0 37
R3
r1
!s85 0
31
Z12 !s108 1573707473.000000
!s107 ..\..\EPT_10M04_AF_UART\src\user_define.v|../../EPT_10M04_AF_UART/src/EPT_10M04_AF_S2_Top.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/src/EPT_10M04_AF_S2_Top.v|
!i113 1
R4
Z13 !s92 +define+SIM -work work
R5
n@e@p@t_10@m04_@a@f_@s2_@top
veptWireOR
Z14 !s110 1573599085
!i10b 1
!s100 <50JgB0^Ul`8^6RgO@LI=1
I>>LW:^8>a[VUR<RjE1kOi2
R1
R0
w1525147696
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/eptWireOR.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/eptWireOR.v
L0 32
R3
r1
!s85 0
31
Z15 !s108 1573599085.000000
!s107 C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/eptWireOR.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/eptWireOR.v|
!i113 1
R4
R5
nept@wire@o@r
vflipflop
Z16 !s110 1573599090
!i10b 1
!s100 blVdT1VOUlzJ7S];Fe71R0
IUk1J5XaW??lX^K7UU9i[M0
R1
R0
w1373324110
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/flipflop.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/flipflop.v
Z17 L0 12
R3
r1
!s85 0
31
Z18 !s108 1573599090.000000
!s107 C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/flipflop.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/flipflop.v|
!i113 1
R4
R5
vhost_ft245_model
Z19 !s110 1573707475
!i10b 1
!s100 R[FP@_@5iRaS30GS?h]go1
IESh?`>3EJ[Uk`5<D;USj^1
R1
R0
Z20 w1520492370
8../../EPT_10M04_AF_UART/test/host_ft245_model.v
F../../EPT_10M04_AF_UART/test/host_ft245_model.v
Z21 L0 14
R3
r1
!s85 0
31
Z22 !s108 1573707475.000000
!s107 ../../EPT_10M04_AF_UART/test/host_ft245_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/test/host_ft245_model.v|
!i113 1
R4
R13
R5
vhost_ft245_model_read
Z23 !s110 1573707476
!i10b 1
!s100 ^9LES9R@U3eM?ci=W29lB3
In4AH`j:^E<24B9;>QECW81
R1
R0
R20
8../../EPT_10M04_AF_UART/test/host_ft245_model_read.v
F../../EPT_10M04_AF_UART/test/host_ft245_model_read.v
Z24 L0 18
R3
r1
!s85 0
31
R22
!s107 ../../EPT_10M04_AF_UART/test/host_ft245_model_read.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/test/host_ft245_model_read.v|
!i113 1
R4
R13
R5
vhost_ft245_model_write
R23
!i10b 1
!s100 kPk>FhCdBR^U4`XW1YE;60
I92boMAA?o62KGbJ64`=Q]0
R1
R0
R20
8../../EPT_10M04_AF_UART/test/host_ft245_model_write.v
F../../EPT_10M04_AF_UART/test/host_ft245_model_write.v
R24
R3
r1
!s85 0
31
Z25 !s108 1573707476.000000
!s107 ../../EPT_10M04_AF_UART/test/host_ft245_model_write.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/test/host_ft245_model_write.v|
!i113 1
R4
R13
R5
vlfsr
Z26 !s110 1573599089
!i10b 1
!s100 n@h;CnZYU6iPAngFhZOGA1
I`J]?BF1Sm]9o0i?z2cK4j1
R1
R0
w1373350450
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/lfsr.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/lfsr.v
R17
R3
r1
!s85 0
31
Z27 !s108 1573599089.000000
!s107 C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/lfsr.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/lfsr.v|
!i113 1
R4
R5
vmem_array
R11
!i10b 1
!s100 4?Se6HKR6S7Nb;C>Z@k>I2
I<g`za;0WZc0D0K?^bS6T<0
R1
R0
w1328652312
8../../EPT_10M04_AF_UART/src/mem_array.v
F../../EPT_10M04_AF_UART/src/mem_array.v
R21
R3
r1
!s85 0
31
R12
!s107 ../../EPT_10M04_AF_UART/src/mem_array.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/src/mem_array.v|
!i113 1
R4
R13
R5
vmemory_mux
R14
!i10b 1
!s100 d[TEiDI@8:@IRMK<]e1Fh1
ICo<@X;]jCU:ZmLRCfo16j1
R1
R0
w1527637840
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/memory_mux.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/memory_mux.v
R2
R3
r1
!s85 0
31
R15
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/memory_mux.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/memory_mux.v|
!i113 1
R4
R5
vmux
R16
!i10b 1
!s100 <fD?3e7hCH@95biek=kJ10
I<D?2[TNFFAkj?kQnAZLJ81
R1
R0
w1373323066
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/mux.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/mux.v
R17
R3
r1
!s85 0
31
R18
!s107 C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/mux.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/mux.v|
!i113 1
R4
R5
vread_control_logic
R11
!i10b 1
!s100 DY9joMQ>IBE[BN1EGF3_n0
I:6nG<z>A6U_I:;Nd5mC6Z2
R1
R0
w1331918130
8../../EPT_10M04_AF_UART/src/read_control_logic.v
F../../EPT_10M04_AF_UART/src/read_control_logic.v
R21
R3
r1
!s85 0
31
R12
!s107 ../../EPT_10M04_AF_UART/src/read_control_logic.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/src/read_control_logic.v|
!i113 1
R4
R13
R5
vserial_uart_comms_model
R19
!i10b 1
!s100 ^Jf;?FLR0nFAQ[j8o9JlD0
I@EK>T8MSnI`Rb4]=^jkjF3
R1
R0
w1573699033
8../../EPT_10M04_AF_UART/test/serial_uart_comms_model.v
F../../EPT_10M04_AF_UART/test/serial_uart_comms_model.v
L0 40
R3
r1
!s85 0
31
R22
!s107 ../Testbench/tb_define.v|../../EPT_10M04_AF_UART/test/serial_uart_comms_model.v|
!s90 +define+SIM|+define+FAST_UART|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/test/serial_uart_comms_model.v|
!i113 1
R4
!s92 +define+SIM +define+FAST_UART -work work
R5
vswitch_control
R8
!i10b 1
!s100 5m=U4K9hb8b:oXdBbbz9c1
IFbXAgefAYT^=E_;07k3CG0
R1
R0
w1527645206
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/switch_control.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/switch_control.v
R9
R3
r1
!s85 0
31
R10
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/switch_control.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/switch_control.v|
!i113 1
R4
R5
vsync_fifo
R11
!i10b 1
!s100 Q7C_UD^9?Vnbj1lb=8bb32
ILWEHX=d1aWflcIlkF?R252
R1
R0
w1331919792
8../../EPT_10M04_AF_UART/src/sync_fifo.v
F../../EPT_10M04_AF_UART/src/sync_fifo.v
R17
R3
r1
!s85 0
31
R12
!s107 ../../EPT_10M04_AF_UART/src/sync_fifo.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/src/sync_fifo.v|
!i113 1
R4
R13
R5
vtb_ept_10M04_top
R23
!i10b 1
!s100 zF5WSfhVdfHm8:W;6Yfa>3
IcOfPi_=D6N0GCfXA4AfNc3
R1
R0
w1573707085
8../../EPT_10M04_AF_UART/Testbench/tb_ept_10M04_top.v
F../../EPT_10M04_AF_UART/Testbench/tb_ept_10M04_top.v
L0 27
R3
r1
!s85 0
31
R25
!s107 ../Testbench/tb_define.v|../../EPT_10M04_AF_UART/Testbench/tb_ept_10M04_top.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/Testbench/tb_ept_10M04_top.v|
!i113 1
R4
R13
R5
ntb_ept_10@m04_top
vuart_iface
R19
!i10b 1
!s100 JV2gFKGXXz]V6I8:V@Io41
Iz0Adi5YiD]C413;Yj4EJW1
R1
R0
R20
8../../EPT_10M04_AF_UART/test/uart_iface.v
F../../EPT_10M04_AF_UART/test/uart_iface.v
L0 36
R3
r1
!s85 0
31
R22
!s107 ../../EPT_10M04_AF_UART/test/uart_iface.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/test/uart_iface.v|
!i113 1
R4
R13
R5
vuart_interface
Z28 !s110 1573707474
!i10b 1
!s100 Bh7bTBe7QF^DFXX[l1fD61
Iag?9g@RIcnG@L@giRd0j41
R1
R0
w1527813700
8../../EPT_10M04_AF_UART/src/uart_interface.v
F../../EPT_10M04_AF_UART/src/uart_interface.v
R2
R3
r1
!s85 0
31
Z29 !s108 1573707474.000000
!s107 ../src/define.v|../../EPT_10M04_AF_UART/src/uart_interface.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/src/uart_interface.v|
!i113 1
R4
R13
R5
vuart_receiver
R19
!i10b 1
!s100 Q:OEEee[k8U93L:dN3fhH1
IAVXPKi2JBoYV7A<mSM8;o1
R1
R0
R20
8../../EPT_10M04_AF_UART/test/uart_receiver.v
F../../EPT_10M04_AF_UART/test/uart_receiver.v
L0 11
R3
r1
!s85 0
31
R22
!s107 ../../EPT_10M04_AF_UART/test/uart_receiver.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/test/uart_receiver.v|
!i113 1
R4
R13
R5
vuart_top
R28
!i10b 1
!s100 MG^f:@oI`C7NLjzZIP_eH2
I3@i:DdMBD?G4@_SW<i9cl2
R1
R0
w1573610374
8../../EPT_10M04_AF_UART/src/uart_top.v
F../../EPT_10M04_AF_UART/src/uart_top.v
L0 24
R3
r1
!s85 0
31
R29
!s107 ../../EPT_10M04_AF_UART/src/uart_top.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/src/uart_top.v|
!i113 1
R4
R13
R5
vuart_transmitter
R28
!i10b 1
!s100 gMYS9?ZoLI667;P>`D1@R1
I5?J^b]@018Y6;a7lQRVX80
R1
R0
R20
8../../EPT_10M04_AF_UART/src/uart_transmitter.v
F../../EPT_10M04_AF_UART/src/uart_transmitter.v
L0 22
R3
r1
!s85 0
31
R29
!s107 ../../EPT_10M04_AF_UART/src/uart_transmitter.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/src/uart_transmitter.v|
!i113 1
R4
R13
R5
vuart_transmitter_model
R19
!i10b 1
!s100 DoQM?H79PYXhFWdEb92?G2
IR_HKSTm>_A]Aga82TD2>K3
R1
R0
R20
8../../EPT_10M04_AF_UART/test/uart_transmitter_model.v
F../../EPT_10M04_AF_UART/test/uart_transmitter_model.v
L0 23
R3
r1
!s85 0
31
R22
!s107 ../../EPT_10M04_AF_UART/test/uart_transmitter_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/test/uart_transmitter_model.v|
!i113 1
R4
R13
R5
vuc_controller
R26
!i10b 1
!s100 KX2U=4;f@o]DI:87KSEl@3
I4]L0dm7VaagSz>NmMFX_l0
R1
R0
w1470808756
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/uc_controller.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/uc_controller.v
L0 30
R3
r1
!s85 0
31
R27
!s107 C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/uc_controller.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/uc_controller.v|
!i113 1
R4
R5
vuc_out_bus
R6
!i10b 1
!s100 dYA>:Nfo7C;fz1_C2g>3g1
I=aCB8jbbWzIPg9DQLdPiN0
R1
R0
w1527897140
8C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/uc_out_bus.v
FC:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/uc_out_bus.v
R2
R3
r1
!s85 0
31
R7
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/uc_out_bus.v|
!s90 -reportprogress|30|-work|work|C:/Jolly/Code_FPGA/EPT_10M04_AF_S2_UART/EPT_10M04_AF_UART/src/uc_out_bus.v|
!i113 1
R4
R5
vwrite_control_logic
R28
!i10b 1
!s100 o3CAmW`OnN9]d;2IzXn6W1
I;_<VQ1;B;EjB`6TVAo]>c0
R1
R0
w1328652014
8../../EPT_10M04_AF_UART/src/write_control_logic.v
F../../EPT_10M04_AF_UART/src/write_control_logic.v
R21
R3
r1
!s85 0
31
R29
!s107 ../../EPT_10M04_AF_UART/src/write_control_logic.v|
!s90 +define+SIM|-reportprogress|300|-work|work|../../EPT_10M04_AF_UART/src/write_control_logic.v|
!i113 1
R4
R13
R5
