m255
K4
z0
!s11f vlog 2020.1 2020.02, Feb 28 2020
vactive_block
Z0 !s110 1737177345
!i10b 1
!s100 [_aU1OT>34GAn8[Re1E;Z0
Z1 !s11b Dg1SIo80bB@j0V0VzS_@n1
I5QTREeZKkeFMHIXLGEl]H2
Z2 VDg1SIo80bB@j0V0VzS_@n1
Z3 dC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/ModelSim
Z4 w1614731350
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_block.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_block.v
!i122 4560
L0 19 332
Z5 OV;L;2020.1;71
r1
!s85 0
31
Z6 !s108 1737177345.000000
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_block.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_block.v|
!i113 1
Z7 o-work work
Z8 !s92 +define+SIM -work work
Z9 tCvgOpt 0
vactive_control_register
R0
!i10b 1
!s100 8:>1L?0EPC:OM=h56HE5S2
R1
IJD6628k7LCGcgWnPGDjJ41
R2
R3
R4
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_control_register.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_control_register.v
!i122 4561
L0 12 87
R5
r1
!s85 0
31
R6
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_control_register.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_control_register.v|
!i113 1
R7
R8
R9
vactive_spi_library
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!i10b 1
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R1
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R2
R3
w1705827073
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_spi_library.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_spi_library.v
!i122 4562
L0 37 170
R5
r1
!s85 0
31
R6
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_spi_library.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_spi_library.v|
!i113 1
R7
R8
R9
vactive_transfer
R10
!i10b 1
!s100 @j_IaA7UmLYSNcbbgGTLB1
R1
IQFmUB9D`?Lz2S?k;Cm1WF3
R2
R3
R4
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_transfer.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_transfer.v
!i122 4563
L0 13 285
R5
r1
!s85 0
31
Z11 !s108 1737177346.000000
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_transfer.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_transfer.v|
!i113 1
R7
R8
R9
vactive_transfer_spi
R10
!i10b 1
!s100 MhCS?c6QVQmL9DzQU1`4L3
R1
IDNoTBLZF1_e7]9dVT95FQ2
R2
R3
w1705990777
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_transfer_spi.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_transfer_spi.v
!i122 4564
L0 33 886
R5
r1
!s85 0
31
R11
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_transfer_spi.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_transfer_spi.v|
!i113 1
R7
R8
R9
vactive_trigger
R10
!i10b 1
!s100 ahz[T=0^?R0VKfnLX:n2Z0
R1
I4nR[TFAU4j3jP@QJS3TaT0
R2
R3
R4
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_trigger.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_trigger.v
!i122 4565
L0 13 106
R5
r1
!s85 0
31
R11
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_trigger.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/active_trigger.v|
!i113 1
R7
R8
R9
vams1115_model
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!i10b 1
!s100 :@]NTYZK2iYfF8FhG]E7n0
R1
IB=JSnES[[V___YdD1iHX`3
R2
R3
w1622574934
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/ams1115_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/ams1115_model.v
!i122 4581
L0 45 581
R5
r1
!s85 0
31
Z13 !s108 1737177348.000000
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/ams1115_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/ams1115_model.v|
!i113 1
R7
R8
R9
vBUFG
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!i10b 1
!s100 0inl:<1km_:ABde3lMRhY0
R1
IXXGhf_1hZFf6RHkAbMH4z0
R2
R3
Z15 w1666776116
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/BUFG.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/BUFG.v
!i122 3636
L0 28 9
R5
r1
!s85 0
31
!s108 1706077627.000000
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/BUFG.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/BUFG.v|
!i113 1
R7
R8
R9
n@b@u@f@g
vendpoint_registers
R10
!i10b 1
!s100 7GKLh3<je<NDfFMPK3oJ42
R1
I:19D9]m<l_31BjTm7XicH3
R2
R3
w1616283291
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/endpoint_registers.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/endpoint_registers.v
!i122 4566
L0 38 715
R5
r1
!s85 0
31
R11
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/endpoint_registers.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/endpoint_registers.v|
!i113 1
R7
R8
R9
vEPT_10CL016_AF_T2_Top
R10
!i10b 1
!s100 TmJdgO4KLlDi;;Q:=Oa]<2
R1
I[HZcofZCA;:5T;jhPI:I83
R2
R3
w1737169034
Z16 8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/EPT_10CL016_AF_T2_Top.v
Z17 FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/EPT_10CL016_AF_T2_Top.v
!i122 4567
L0 33 1231
R5
r1
!s85 0
31
R11
Z18 !s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/EPT_10CL016_AF_T2_Top.v|
Z19 !s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/EPT_10CL016_AF_T2_Top.v|
!i113 1
R7
R8
R9
n@e@p@t_10@c@l016_@a@f_@t2_@top
veptWireOR
R10
!i10b 1
!s100 UaJTo1NoeWCN>z>QnFLV@1
R1
I@Q4<izd:TcI62k6T7`LzO3
R2
R3
w1341557582
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/eptWireOR.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/eptWireOR.v
!i122 4568
L0 32 14
R5
r1
!s85 0
31
R11
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/eptWireOR.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/eptWireOR.v|
!i113 1
R7
R8
R9
nept@wire@o@r
vfifo_4x16_model
R12
!i10b 1
!s100 l9RzhGh>bI66SDmAFPXgA2
R1
I`:dLL[P1bF8@]G1i[TP6a3
R2
R3
R4
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/fifo_4x16_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/fifo_4x16_model.v
!i122 4582
L0 38 328
R5
r1
!s85 0
31
R13
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/fifo_4x16_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/fifo_4x16_model.v|
!i113 1
R7
R8
R9
vft_245_state_machine
Z20 !s110 1737177347
!i10b 1
!s100 @DDff?:^SC>kbI@;kRMKR0
R1
InMJ2_LkTB@Sz5CAR:UB?90
R2
R3
w1705908872
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/ft_245_state_machine.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/ft_245_state_machine.v
!i122 4569
L0 41 436
R5
r1
!s85 0
31
Z21 !s108 1737177347.000000
!s107 ../src/define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/ft_245_state_machine.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/ft_245_state_machine.v|
!i113 1
R7
R8
R9
vHDMI_Clock
Z22 !s110 1706077629
!i10b 1
!s100 OZQJVhmWe?MYod4gc9?V31
R1
I3d[MKgzh7RcCF3eYfeV2E0
R2
R3
w1666894488
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/HDMI_Clock.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/HDMI_Clock.v
!i122 3641
L0 32 66
R5
r1
!s85 0
31
Z23 !s108 1706077629.000000
!s107 ../Testbench/tb_define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/HDMI_Clock.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/HDMI_Clock.v|
!i113 1
R7
R8
R9
n@h@d@m@i_@clock
vhost_ft245_model
R12
!i10b 1
!s100 :6afL12NO=OaZL1VTSYg_0
R1
IfFMianck9kJQa2B`NEREF2
R2
R3
w1704848161
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model.v
!i122 4583
L0 39 680
R5
r1
!s85 0
31
R13
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model.v|
!i113 1
R7
R8
R9
vhost_ft245_model_read
R12
!i10b 1
!s100 GFW<NfW]JPP>TAh[AM=Gc3
R1
I2gzz0haMC4hKLb73fmN0N1
R2
R3
w1340088422
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model_read.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model_read.v
!i122 4584
L0 18 299
R5
r1
!s85 0
31
R13
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model_read.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model_read.v|
!i113 1
R7
R8
R9
vhost_ft245_model_write
R12
!i10b 1
!s100 Ek5J`CG8F>a;?1ILI@C^k0
R1
IoPXo3B860m>gmY7PRPbVB2
R2
R3
w1341987916
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model_write.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model_write.v
!i122 4585
L0 18 353
R5
r1
!s85 0
31
R13
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model_write.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_ft245_model_write.v|
!i113 1
R7
R8
R9
vhost_image_block_in
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!i10b 1
!s100 Ejk@4T`:X89RFKakUZ?_32
R1
IBz?F9f?CRgM2[DQN;MB4i0
R2
R3
w1558739076
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_image_block_in.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_image_block_in.v
!i122 4586
L0 28 173
R5
r1
!s85 0
31
R13
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_image_block_in.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/host_image_block_in.v|
!i113 1
R7
R8
R9
vi2c_ack_model
R24
!i10b 1
!s100 ZVJhl?c2KRGNg[jDT9Scz1
R1
I67BT<3_84b<L_V20BV2A40
R2
R3
w1470189102
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_ack_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_ack_model.v
!i122 4587
L0 31 430
R5
r1
!s85 0
31
Z25 !s108 1737177349.000000
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_ack_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_ack_model.v|
!i113 1
R7
R8
R9
vi2c_receive_model
R24
!i10b 1
!s100 nlLRFh1YJ>5^0>In5N^oN0
R1
IMOY]cTh_73T[PJhziGmBA3
R2
R3
w1470189112
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_receive_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_receive_model.v
!i122 4588
L0 30 309
R5
r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_receive_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_receive_model.v|
!i113 1
R7
R8
R9
vi2c_slave_comms_model
R24
!i10b 1
!s100 QjP<ZAdOX>K7[E3zMTD7I0
R1
Il74TIo`<O@OfnYK2^Mf0H2
R2
R3
w1470678096
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_slave_comms_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_slave_comms_model.v
!i122 4589
L0 28 1136
R5
r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_slave_comms_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_slave_comms_model.v|
!i113 1
R7
R8
R9
vi2c_transmit_model
R24
!i10b 1
!s100 ?:l24:CPVDm6SOn2D^I2i3
R1
I5B;Kj4SIdje0jQbm4dzh?3
R2
R3
w1470437176
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_transmit_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_transmit_model.v
!i122 4590
L0 27 175
R5
r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_transmit_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/i2c_transmit_model.v|
!i113 1
R7
R8
R9
vmem_array
R24
!i10b 1
!s100 :hFU2zWNOGdG1]d0D@Q=A1
R1
I3h[XHeRFDf8YcHVX8dKD>1
R2
R3
w1328652312
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/mem_array.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/mem_array.v
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r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/mem_array.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/mem_array.v|
!i113 1
R7
R8
R9
vmux
R20
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IzNCQTS6IeME:S<ai_SN_M0
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w1373323066
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/mux.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/mux.v
!i122 4571
L0 12 21
R5
r1
!s85 0
31
R21
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/mux.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/mux.v|
!i113 1
R7
R8
R9
vOBUFDS
R22
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IX1US4oO[[i_=gJ[6@;UnD1
R2
R3
R15
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/OBUFDS.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/OBUFDS.v
!i122 3644
Z26 L0 28 15
R5
r1
!s85 0
31
R23
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/OBUFDS.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/OBUFDS.v|
!i113 1
R7
R8
R9
n@o@b@u@f@d@s
vOBUFG
R22
!i10b 1
!s100 :bi>KHMj2GXPaC``<Hm<B1
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IQ8oIag5_[_]0lPoM_LgeD0
R2
R3
R15
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/OBUFG.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/OBUFG.v
!i122 3645
R26
R5
r1
!s85 0
31
R23
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/OBUFG.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/OBUFG.v|
!i113 1
R7
R8
R9
n@o@b@u@f@g
vread_control_logic
R24
!i10b 1
!s100 2bkeFNH6gb3PoaPH::Ven2
R1
IG5D;<NU5:Z4=Ld09FoJP10
R2
R3
w1331918130
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/read_control_logic.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/read_control_logic.v
!i122 4593
L0 14 57
R5
r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/read_control_logic.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/read_control_logic.v|
!i113 1
R7
R8
R9
vread_SPI
R24
!i10b 1
!s100 II[<aTj0O@hM5^A=<hS2Y0
R1
I7zS[0MgZ<7JAMmm^`BA<03
R2
R3
w1439627996
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/read_SPI.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/read_SPI.v
!i122 4594
L0 15 215
R5
r1
!s85 0
31
R25
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/read_SPI.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/read_SPI.v|
!i113 1
R7
R8
R9
nread_@s@p@i
vread_SPI_master
R20
!i10b 1
!s100 L2ddb7CH1Vf01fA[eB_WU0
R1
I6]=jig1NoTP7Z3gjF80[L0
R2
R3
w1704334555
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/read_SPI_master.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/read_SPI_master.v
!i122 4573
L0 15 234
R5
r1
!s85 0
31
R21
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/read_SPI_master.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/read_SPI_master.v|
!i113 1
R7
R8
R9
nread_@s@p@i_master
vrgb_led_control
R20
!i10b 1
!s100 zJR:O2nKGS@QU8[gn1BUm2
R1
IjQ;>MA7F9>gXN6ml2=cMV1
R2
R3
w1737169819
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/rgb_led_control.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/rgb_led_control.v
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L0 28 419
R5
r1
!s85 0
31
R21
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/rgb_led_control.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/rgb_led_control.v|
!i113 1
R7
R8
R9
vserial_clock
R20
!i10b 1
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IRdfPGk3eU?3XVC>1?1YVM1
R2
R3
w1627528384
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/serial_clock.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/serial_clock.v
!i122 4575
L0 30 50
R5
r1
!s85 0
31
R21
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/serial_clock.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/serial_clock.v|
!i113 1
R7
R8
R9
vseven_segment_led_display
R20
!i10b 1
!s100 ZW8HeHIEdIJ;nCn7UVlol0
R1
I;5N`kaM[6n^@naPSC@cF52
R2
R3
w1737153261
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/seven_segment_led_display.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/seven_segment_led_display.v
!i122 4576
L0 28 532
R5
r1
!s85 0
31
R21
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/seven_segment_led_display.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/seven_segment_led_display.v|
!i113 1
R7
R8
R9
vslave_spi_comms_model
Z27 !s110 1737177350
!i10b 1
!s100 RWTPjVU72SBFWO;SO@22c2
R1
IWf^`XF8EKG9:^J2;nl`@e1
R2
R3
w1705988788
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/slave_spi_comms_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/slave_spi_comms_model.v
!i122 4595
L0 40 713
R5
r1
!s85 0
31
R25
!s107 ../Testbench/tb_define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/slave_spi_comms_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/slave_spi_comms_model.v|
!i113 1
R7
R8
R9
vslave_spi_iface_model
R27
!i10b 1
!s100 mX;U;ij7Q;nl[HP3h]RB<2
R1
I6OiZUiz_N1S8NL2<jLFJQ2
R2
R3
w1705359671
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/slave_spi_iface_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/slave_spi_iface_model.v
!i122 4596
L0 14 600
R5
r1
!s85 0
31
Z28 !s108 1737177350.000000
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/slave_spi_iface_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/slave_spi_iface_model.v|
!i113 1
R7
R8
R9
vspi_iface_master
R12
!i10b 1
!s100 lF2>41dFZ@7B4cz:8ThGU0
R1
I_MI37YNji:RLZGEi^j3PW1
R2
R3
w1704937906
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/spi_iface_master.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/spi_iface_master.v
!i122 4577
L0 13 505
R5
r1
!s85 0
31
R21
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/spi_iface_master.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/spi_iface_master.v|
!i113 1
R7
R8
R9
vspi_tiny_slave_model
R27
!i10b 1
!s100 XhacP5;KPMhNGzddU;6B30
R1
IPNE>W<RH<YmK;<gQFfzgj1
R2
R3
w1702448390
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/spi_tiny_slave_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/spi_tiny_slave_model.v
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L0 13 502
R5
r1
!s85 0
31
R28
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/spi_tiny_slave_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/spi_tiny_slave_model.v|
!i113 1
R7
R8
R9
vsync_fifo
R27
!i10b 1
!s100 4XVYIXkQJNZ9P`foKLHRV3
R1
I6ZTXR270nb;H5f^zNgZH43
R2
R3
w1331919792
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/sync_fifo.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/sync_fifo.v
!i122 4598
L0 12 82
R5
r1
!s85 0
31
R28
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/sync_fifo.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/sync_fifo.v|
!i113 1
R7
R8
R9
vtb_ept_10cl016_top
!s110 1737177351
!i10b 1
!s100 Udeo>22Vn0n89MN2]73XU2
R1
IL><IO<nOKLaJ1oJlAQeD>0
R2
R3
w1737177336
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/Testbench/tb_ept_10cl016_top.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/Testbench/tb_ept_10cl016_top.v
!i122 4604
L0 28 2175
R5
r1
!s85 0
31
!s108 1737177351.000000
!s107 ../src/cycloprologic_define.v|../Testbench/tb_define.v|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/Testbench/tb_ept_10cl016_top.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/Testbench/tb_ept_10cl016_top.v|
!i113 1
R7
R8
R9
vTMDS_encoder
R14
!i10b 1
!s100 o]Co2ZOh6Zk85[PdJFMcS2
R1
IkRi>HU8aBaJOD8QUL722e2
R2
R3
w1706076489
R16
R17
!i122 3638
L0 1041 24
R5
r1
!s85 0
31
!s108 1706077628.000000
R18
R19
!i113 1
R7
R8
R9
n@t@m@d@s_encoder
vuart_iface
R27
!i10b 1
!s100 Gh4X3;]TjR0EPU^n0GgF60
R1
I7lN7TFkcB2bDdOmHEAZPk0
R2
R3
Z29 w1614731351
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_iface.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_iface.v
!i122 4599
L0 36 59
R5
r1
!s85 0
31
R28
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_iface.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_iface.v|
!i113 1
R7
R8
R9
vuart_receiver
R27
!i10b 1
!s100 CaEIJ[QP1QWC5ehWLdEYL1
R1
Io17gZ>]CkPe8gG0KXcY]31
R2
R3
R29
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_receiver.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_receiver.v
!i122 4600
L0 11 239
R5
r1
!s85 0
31
R28
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_receiver.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_receiver.v|
!i113 1
R7
R8
R9
vuart_transmitter_model
R27
!i10b 1
!s100 5[afZUQ]z0?WT5neSCX7b2
R1
Ib=mIXnn;7a<_i3i3>5o?42
R2
R3
R29
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_transmitter_model.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_transmitter_model.v
!i122 4601
L0 23 180
R5
r1
!s85 0
31
R28
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_transmitter_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/uart_transmitter_model.v|
!i113 1
R7
R8
R9
vwrite_control_logic
R27
!i10b 1
!s100 ZZfUVoPnGLV?1heZLf^lH2
R1
IM9MYTVlgCOZ99QQ<<=BRf2
R2
R3
w1328652014
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/write_control_logic.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/write_control_logic.v
!i122 4602
L0 14 68
R5
r1
!s85 0
31
R28
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/write_control_logic.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/write_control_logic.v|
!i113 1
R7
R8
R9
vwrite_SPI
R27
!i10b 1
!s100 lOh]B:8OnnQK6CDiL]GWR2
R1
IoI8_j^FaSNDVf=Tfz]H:S1
R2
R3
w1439628013
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/write_SPI.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/write_SPI.v
!i122 4603
L0 16 207
R5
r1
!s85 0
31
R28
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/write_SPI.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/test/write_SPI.v|
!i113 1
R7
R8
R9
nwrite_@s@p@i
vwrite_SPI_master
R12
!i10b 1
!s100 bF;hSO3g?Q5n9hY2OQgVZ0
R1
I_`n;fF1bgJEH`7NHkU_z@0
R2
R3
w1692503484
8C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/write_SPI_master.v
FC:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/write_SPI_master.v
!i122 4580
L0 15 228
R5
r1
!s85 0
31
R13
!s107 C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/write_SPI_master.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_10CL016_CB_System_Demo/EPT_10CL016_CB_System_Demo/src/write_SPI_master.v|
!i113 1
R7
R8
R9
nwrite_@s@p@i_master
