m255
K4
z2
!s11f vlog 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
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cModel Technology
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!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/src/active_block.v|
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!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/src/active_control_register.v|
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!s107 C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/fifo_4x16_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/fifo_4x16_model.v|
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!s90 -reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Serial_Transfer/EPT_4CE6_AF_Serial_Transfer/src/flipflop.v|
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!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/src/ft_245_state_machine.v|
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FC:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/mem_array.v
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!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/mem_array.v|
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vmux
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w1373323066
8C:/Jolly/Code_FPGA/EPT_4CE6_AF_Serial_Transfer/EPT_4CE6_AF_Serial_Transfer/src/mux.v
FC:/Jolly/Code_FPGA/EPT_4CE6_AF_Serial_Transfer/EPT_4CE6_AF_Serial_Transfer/src/mux.v
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r1
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R23
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vread_control_logic
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8C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/read_control_logic.v
FC:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/read_control_logic.v
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!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/read_control_logic.v|
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vserial_clock
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R4
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vsync_fifo
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8C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/sync_fifo.v
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R8
R9
vtb_ept_4ce6_top
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R4
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8C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/uart_iface.v
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R9
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R26
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R3
R4
R27
8C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/uart_receiver.v
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!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/uart_receiver.v|
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R8
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vuart_top
R15
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IdjDMe4]cV6c4z[:T?L_Pc0
R3
R4
R5
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FC:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/src/uart_top.v
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R9
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IK5_h2XOcfzgCJoMeaXg@B2
R3
R4
R5
8C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/src/uart_transmitter.v
FC:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/src/uart_transmitter.v
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L0 22 180
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31
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!s107 C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/src/uart_transmitter.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/src/uart_transmitter.v|
!i113 1
R7
R8
R9
vuart_transmitter_model
R24
!i10b 1
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ISY]kgbXBo;P0Ylj1J_RdR1
R3
R4
R27
8C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/uart_transmitter_model.v
FC:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/uart_transmitter_model.v
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r1
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31
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!s107 C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/uart_transmitter_model.v|
!s90 +define+SIM|-reportprogress|300|-work|work|C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/uart_transmitter_model.v|
!i113 1
R7
R8
R9
vwrite_control_logic
R24
!i10b 1
!s100 ZZfUVoPnGLV?1heZLf^lH2
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IH2gWK:GGYPP4JkT26>Xc_3
R3
R4
w1328652014
8C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/write_control_logic.v
FC:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/write_control_logic.v
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r1
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!s107 C:/Jolly/Code_FPGA/EPT_4CE6_AF_Platform_Demo/EPT_4CE6_AF_Platform_Demo/test/write_control_logic.v|
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!i113 1
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